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256-position spi/i 2 c selectable digital potentiometer ad5161 rev. 0 in fo rmation fur n ished by an al o g d e v i c e s is believed t o be accurate an d r e liable. how e ver, no r e spon sibili ty is assumed by anal og de vices fo r its use, nor for a n y i n fri n geme nt s of p a t e nt s or ot h e r ri g h t s o f th ird parties that m a y res u lt fro m its use . s p ecificatio n s subj ec t to chan ge witho u t n o tice. no licen s e is g r an te d b y implicatio n or ot h e rwi s e u n de r any p a t e nt or p a t e nt ri ght s of a n al og de vi c e s. tra d emark s a n d registered tra d ema r ks are the proper ty of th eir respectiv e co mpan ies. one technolog y way, p.o . box 9106, norwood, ma 02062-9106, u.s.a. t e l: 781. 329. 4 700 www.analog.com fax: 781. 326. 87 03 ? 2003 analog de vices, i n c. al l r i ght s r e ser v ed . fea t ures 256-position end-to-end r e s istance 5 k?, 1 0 k?, 50 k?, 10 0 k? compact msop-10 ( 3 mm 4. 9 mm) package pin selectable spi/i 2 c compati b le interface extra package address decod e pin ad 0 full re ad/write of wiper register power-on preset to midscale single supply 2 . 7 v to 5. 5 v low temperature coefficient 4 5 ppm/c low power, i dd = 8 a wide operatin g temperature C40c to + 125 c sdo output all o ws multiple device daisy-cha ining evaluation board available a pplic a t io ns mechanical pot e ntiometer replacement in ne w designs transducer adj u stment of pre ssure, tempera t ure, position, chemical, and optical sensors rf amplifier bi asing automotive e l ectronics adjustment gain control and offset a d just ment gener a l ov er view the ad5161 p r o v ides a com p ac t 3 mm 4.9 mm p a c k a g e d s o l u tio n f o r 256-p o si tio n ad j u s t m e n t a p p l ic a t ion s . th es e de vices p e r f or m t h e s a me el e c t r on i c a d j u st me n t f u nc t i on a s me ch an i c a l p o te n t i o me te rs or v a r i abl e re s i stors , w i t h e n h a nc e d re s o lut i on, s o lid-st a t e r e l i ab i l i t y , an d s u p e r i o r lo w t e m p era t ur e co ef f i cien t pe rf o r m a n c e . the wi p e r s e t t i n gs a r e co n t r o l l a b l e t h r o ug h a p i n s e le c t a b le sp i or i 2 c co m p a t i b le dig i ta l in t e r f ace , which can als o be us e d t o r e ad bac k t h e wi p e r r e g i s t er con t en t. w h en t h e s p i m o de is us e d , t h e de vic e ca n b e da i s y - ch a i ne d (sd o to sdi), a l lo win g s e v e ral p a r t s t o s h a r e the s a m e co n t r o l lin e s. i n th e i 2 c m o de , addr ess p i n ad 0 ca n b e us e d to place u p to tw o de vices on t h e s a me b u s. i n t h i s s a me m o de, c o mman d b i ts a r e a v a i la b l e to r e s e t th e wi p e r p o si tio n t o mids cale o r t o s h u t do wn t h e de vic e in t o a st a t e o f z e r o p o w e r co n s um p t ion. o p era t ing f r o m a 2.7 v t o 5.5 v p o w e r s u p p l y a nd co n s u m in g l e ss t h an 5 a a l l o w s for u s age i n p o r t abl e b a t t e r y - op e r a t e d ap p l i c at i o n s . func ti onal bl oc k di a g ram wiper register sdi/sda clk/scl dis cs/ad0 gnd sdo/nc v dd a w b spi or i 2 c interface fi g u r e 1 . pin c o n f igur a t ion 1 2 3 4 5 10 9 8 7 6 a b cs/ado sdo/nc sdi/sd a dd ad5161 top view (not to scale) w v dis gnd clk/s c l fi g u r e 2 . note: the terms di gital potentiometer , vr , and rdac are use d inte rchange a bl y. purc hase of l i c e nse d i 2 c c o mp on ent s of a n al og devi c e s o r on e of i t s sub l i c ensed associated c o mpani e s conv eys a license f o r the purcha ser un d e r the philips i 2 c paten t rig h ts to use th ese co mpon en ts in an i 2 c system , provi d ed th at the system co n f o r ms to th e i 2 c stan d a r d s p ecificatio n as d e fin e d by p h ilips.
ad5161 rev. 0 | page 2 of 2 0 table of contents electrical characteristics?5 k version ...................................... 3 electrical characteristics?10 k, 50 k, 100 k versions ....... 4 timing characteristics?5 k, 10 k, 50 k, 100 k versions 5 absolute maximum ratings 1 .......................................................... 6 typical performance characteristics ............................................. 7 test circuits ..................................................................................... 11 spi interface .................................................................................... 12 i 2 c interface ..................................................................................... 13 operation ......................................................................................... 14 programming the variable resistor ......................................... 14 programming the potentiometer divider ............................... 15 pin selectable digital interface ................................................. 15 level shifting for bidirectional interface ................................ 17 esd protection ........................................................................... 17 terminal voltage operating range .......................................... 17 power-up sequence ................................................................... 17 layout and power supply bypassing ....................................... 17 pin configuration and function descriptions ........................... 18 pin configuration ...................................................................... 18 pin function descriptions ........................................................ 18 outline dimensions ....................................................................... 19 ordering guide .......................................................................... 19 esd caution ................................................................................ 19 revision history revision 0: initial version
ad5161 rev. 0 | page 3 of 20 electrical characteristics?5 k version (v dd = 5 v 10%, or 3 v 10%; v a = +v dd ; v b = 0 v; ?40c < t a < +125c; unless otherwise noted.) table 1. parameter symbol conditions min typ 1 max unit dc characteristics?rheostat mode resistor differential nonlinearity 2 r-dnl r wb , v a = no connect ?1.5 0.1 +1.5 lsb resistor integral nonlinearity 2 r-inl r wb , v a = no connect ?4 0.75 +4 lsb nominal resistor tolerance 3 r ab t a = 25c ?30 +30 % resistance temperature coefficient r ab /t v ab = v dd , wiper = no connect 45 ppm/c wiper resistance r w 50 120 dc characteristics?potentiometer divider mode (specifications apply to all vrs) resolution n 8 bits differential nonlinearity 4 dnl ?1.5 0.1 +1.5 lsb integral nonlinearity 4 inl ?1.5 0.6 +1.5 lsb voltage divider temperature coefficient v w /t code = 0x80 15 ppm/c full-scale error v wfse code = 0xff ?6 ?2.5 0 lsb zero-scale error v wzse code = 0x00 0 +2 +6 lsb resistor terminals voltage range 5 v a,b,w gnd v dd v capacitance 6 a, b c a,b f = 1 mhz, measured to gnd, code = 0x80 45 pf capacitance 6 w c w f = 1 mhz, measured to gnd, code = 0x80 60 pf shutdown supply current 7 i dd_sd v dd = 5.5 v 0.01 1 a common-mode leakage i cm v a = v b = v dd /2 1 na digital inputs and outputs input logic high v ih 2.4 v input logic low v il 0.8 v input logic high v ih v dd = 3 v 2.1 v input logic low v il v dd = 3 v 0.6 v input current i il v in = 0 v or 5 v 1 a input capacitance 6 c il 5 pf power supplies power supply range v dd range 2.7 5.5 v supply current i dd v ih = 5 v or v il = 0 v 3 8 a power dissipation 8 p diss v ih = 5 v or v il = 0 v, v dd = 5 v 0.2 mw power supply sensitivity pss v dd = +5 v 10%, code = midscale 0.02 0.05 %/% dynamic characteristics 6, 9 bandwidth ?3db bw_5k r ab = 5 k, code = 0x80 1.2 mhz total harmonic distortion thd w v a = 1 v rms, v b = 0 v, f = 1 khz 0.05 % v w settling time t s v a = 5 v, v b = 0 v, 1 lsb error band 1 s resistor noise voltage density e n_wb r wb = 2.5 k, rs = 0 6 nv/hz
ad5161 electrical characteristics10 k?, 50 k?, 100 k? versions (v dd = 5 v 10 %, o r 3 v 10%; v a = v dd ; v b = 0 v ; C40c < t a < +125c; unles s o t h e r w is e n o ted . ) table 2. p a r a m e t e r s y m b o l c o n d i t i o n s m i n typ 1 m a x u n i t dc charac teri sticsrheos t at mode resistor differential nonlin earit y 2 r - d n l r wb , v a = no con n ect C1 0.1 +1 lsb resistor integral nonlinearity 2 r - i n l r wb , v a = no con n ect C2 0.25 +2 lsb nominal resi sto r t o lerance 3 ? r ab t a = 25c C30 +30 % resistance tem p erature coefficient ?r ab /?t v ab = v dd , wiper = no connect 4 5 p p m / c wiper resistanc e r w v dd = 5 v 50 120 ? dc charac teri sticspote ntiometer divid e r mode (specifications a pply to all vrs) resolution n 8 b i t s differential non l inearity 4 d n l C 1 0 . 1 + 1 l s b integral nonlinearity 4 i n l C 1 0 . 3 + 1 l s b voltage divider temperature coefficient ?v w /?t code = 0x80 15 ppm/c full-scale error v wfs e code = 0xff C3 C1 0 lsb zero-scale err o r v wzs e code = 0x00 0 1 3 lsb resistor termi n als voltage range 5 v a,b,w g n d v dd v capacitance 6 a, b c a,b f = 1 mhz, measured to gnd, code = 0x80 4 5 p f capacitance 6 w c w f = 1 mhz, measured to gnd, code = 0x80 6 0 p f shutdown supply current 7 i dd_sd v dd = 5.5 v 0.01 1 a common-mode leakage i cm v a = v b = v dd / 2 1 n a digital inpu ts and outpu t s input logic hig h v ih 2 . 4 v input logic low v il 0 . 8 v input logic hig h v ih v dd = 3 v 2.1 v input logic low v il v dd = 3 v 0.6 v input current i il v in = 0 v or 5 v 1 a input capacitance 6 c il 5 p f power suppli e s power supply range v dd ran g e 2 . 7 5 . 5 v supply current i dd v ih = 5 v or v il = 0 v 3 8 a power dissi pati on 8 p diss v ih = 5 v or v il = 0 v, v dd = 5 v 0 . 2 m w power supply s e nsitivity pss ?v dd = +5 v 10%, code = mids cale 0 . 0 2 0 . 0 5 % / % dynamic ch aracteris t ics 6, 9 bandwidth C3db b w r ab = 10 k?/50 k?/100 k?, code = 0x80 6 0 0 / 1 0 0 / 4 0 k h z t o tal harmonic distortion t h d w v a =1 v rms, v b = 0 v, f = 1 khz, r ab = 10 k? 0 . 0 5 % v w settling time (10 k?/50 k?/100 k?) t s v a = 5 v, v b = 0 v, 1 lsb error band 2 s resistor noise v o ltage density e n_wb r wb = 5 k?, rs = 0 9 nv/hz rev. 0 | page 4 of 2 0
ad5161 timing characteristics5 k?, 10 k?, 50 k?, 100 k? versions (v dd = +5v 1 0 % , o r +3v 10% ; v a = v dd ; v b = 0 v ; C40c < t a < +125c; unles s o t h e r w is e n o ted . ) table 3. p a r a m e t e r s y m b o l c o n d i t i o n s m i n typ 1 max unit spi in terface timing c harac teris t ics 6, 10 (spe cifications apply to all parts) clock fre quenc y f clk 2 5 m h z input clock puls ewidth t ch , t cl clock level hig h or low 20 ns data setup tim e t ds 5 n s data hold time t dh 5 n s cs setup time t css 1 5 n s cs high pulsewidth t csw 4 0 n s clk fall to cs fall hold t ime t csh0 0 n s clk fall to cs rise hold time t csh1 0 n s cs rise to clock rise setup t cs1 1 0 n s i 2 c inte rface timing c harac teris t ics 6, 11 (spe cifications apply to all parts) scl clock frequ ency f scl 4 0 0 k h z t bu f bus free ti me between stop and start t 1 1 . 3 s t hd;sta hold time (repeated sta r t) t 2 after this period, the first clock p u lse is generated. 0 . 6 s t low low period of scl clock t 3 1 . 3 s t high high period of scl clock t 4 0 . 6 5 0 s t su ;st a se tup tim e for repeated start condition t 5 0 . 6 s t hd;dat data hold time t 6 0 . 9 s t su ;dat data setu p time t 7 1 0 0 n s t f fall time of both sda and sc l signals t 8 3 0 0 n s t r rise time of both sda and sc l signals t 9 3 0 0 n s t su ;st o set u p tim e for stop condition t 10 0 . 6 s notes 1 typical s p ecif ications repres ent avera g e read ings at + 25c and v dd = 5 v. 2 r e si st o r po si t i on n o n l i n ea ri t y error r - in l i s t h e devi a t i o n f r om an ideal val u e meas ured betw een the maximum re si s t a n ce a n d t h e m i n im um resi st a n ce wi per posi t i on s. r - d n l m e a s ure s t h e rela t i ve st ep ch a n ge from i d ea l bet w een succ essi ve t a p posi t i on s . pa rt s a r e gua ra n t eed m o n o t o n i c. 3 v ab = v dd , w i p e r ( v w ) = no co nne ct. 4 inl and dnl are m e as ured at v w with the rda c c o nf igured a s a p o tentiometer d i vid e r s imil ar to a vol t age output d/a converter. va = v dd a n d v b = 0 v. dnl s p ecif ication l i mits of 1 l s b maximum ar e guarante e d m o no to nic o p e r ating co nd itio ns . 5 res i s t or terminal s a , b, w have no l imitations on pol a ri ty with res p ect to eac h other. 6 gua r a n t eed by des i gn a n d n o t subj ect t o pro d uct i on t e st . 7 mea s ure d a t t h e a t e rm i n a l . th e a t e r m i n a l i s open ci rcui t e d i n sh ut d o wn m o de. 8 p diss i s ca lcula t e d fr om (i dd v dd ). cmo s l o gi c leve l i n put s resu lt in minimum power d i ss ipation. 9 al l d y namic characteris t ics use v dd = 5 v. 10 see timing d iagram f o r location of meas ured values. a l l i n put control vol t ages are s p ecif ied wit h t r = t f = 2 n s (10% t o 90% of 3 v ) a n d t i m e d fr om a vo lt a g e level of 1.5 v. 11 see timing d iagrams for l o cations of meas ured val u es . rev. 0 | page 5 of 2 0
ad5161 rev. 0 | page 6 of 20 absolute maximum ratings 1 (t a = +25c, unless otherwise noted.) table 4 parameter value v dd to gnd ?0.3 v to +7 v v a , v b , v w to gnd v dd i max 1 20 ma digital inputs and output vo ltage to gnd 0 v to +7 v operating temperature range ?40c to +125c maximum junction temperature (t jmax ) 150c storage temperature ?65c to +150c lead temperature (soldering, 10 sec) 300c thermal resistance 2 ja : msop-10 200c/w notes 1 maximum terminal current is bounde d by the maximum current handling of the switches, maximum power dissip ation of the package, and maximum applied voltage across any two of the a, b, and w terminals at a given resistance. 2 package power dissipation = (t jmax ? t a )/ ja . stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ad5161 typical perf orm ance cha r acte ristics code (decimal) ?1.0 ?0.8 ?0.6 ? 0.4 ? 0.2 0 0.2 0.4 0.6 1.0 32 09 6 64 128 160 192 224 256 rheostat mode inl (lsb) 0.8 5v 3v f i gur e 3 . r - inl vs . co de vs . sup p l y v o l t a g e s 5v 3v ? 1.0 ? 0.8 ? 0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 1.0 rhe os tat mode dnl (ls b ) 0.8 code (decimal) 32 09 6 64 128 160 192 224 256 f i gur e 4 . r - dnl vs . c o de vs . sup p l y v o lta g e s _ 40c +25 c +85c +125 c ?1.0 ?0.8 ?0.6 ? 0.4 ? 0.2 0 0.2 0.4 0.6 1.0 p o te ntiome te r mode inl (ls b ) 0.8 code (decimal) 32 09 6 64 128 160 192 224 256 f i gure 5. inl vs. code , v dd = 5 v code (decimal) ? 1.0 ? 0.8 ? 0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 1.0 32 09 6 64 128 160 192 224 256 p o te ntiome te r mode dnl (ls b ) 0.8 ?4 0 c +25c +85 c +125c f i gure 6. dnl vs. c o de , v dd = 5 v ?1.0 ? 0.8 ? 0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 1.0 p o te ntiome te r mode inl (ls b ) 0.8 code (decimal) 32 09 6 64 128 160 192 224 256 5v 3v f i gur e 7 . inl vs . code vs . sup p l y v o l t age s 5v 3v code (decimal) ?1.0 ?0.8 ? 0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 32 09 6 64 128 160 192 224 256 p o te ntiome te r mode dnl(ls b ) 1.0 f i gur e 8 . dnl vs . c o de vs . sup p l y v o l t a g e s rev. 0 page 7 of 2 0
ad5161 rev. 0 | page 8 of 2 0 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 1.0 rheostat m o de inl (lsb) 0.8 code (decimal) 32 09 6 64 128 160 192 224 256 c +25 c +85c +1 2 5 c ?40 f i gure 9. r-inl vs. code , v dd = 5 v ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 1.0 rhe os tat mode dnl (ls b ) 0.8 code (decimal) 32 09 6 64 128 160 192 224 256 _ 40 c +25c +85c +125c f i gure 10. r-dnl vs. c o d e , v dd = 5 v temperature (c) 0 4 0 8 0 120 ?4 0 0 1.5 fse, fu ll- sc a l e er r o r ( l sb ) 0 4 0 8 0 120 ?4 0 1.0 2.5 v dd = 5.5v v dd = 2.7v 2.0 0.5 f i gure 11. f u ll- s c al e e rror v s . t e m p er a t ur e 0 4 0 8 0 120 ?4 0 0 1.5 zs e , ze ro-s cale e rror ( a) temperature (c) 0 4 0 8 0 120 ?4 0 1.0 2.5 v dd = 5.5v v dd = 2.7v 2.0 0.5 f i gure 12. zero -s c a le e r r o r v s . t e mpe r a t ur e temperature (c) 0 4 0 8 0 120 ?4 0 0.1 1 10 i dd s u p p l y curre nt ( a) v dd = 5.5v v dd = 2.7v f i gure 13. sup p l y current v s . t e mper at ur e i a s hutdown curre nt (na) temperature ( c ) 0 0 70 20 10 30 40 50 60 40 80 120 ?40 v dd = 5v f i gure 14. sh u t do w n cur r ent v s . t e mper atu r e
ad5161 rev. 0 | page 9 of 2 0 code (decimal) ?50 0 50 100 150 200 32 09 6 64 128 160 192 224 256 rheostat mode tempco (ppm/c) fi g ure 15. r h e o s t at m o de t e m p co ?r wb / ?t v s . code code (decimal) ?20 0 20 40 60 80 100 120 140 160 32 09 6 64 128 160 192 224 256 p o te ntiome te r mode te mp co (ppm/c) fi g ure 1 6 . p o tentiom e ter m o de t e m p co ? v wb / ?t v s . cod e 1k 10k 100k 1m 0 ?6 ?1 2 ?1 8 ?2 4 ?3 0 ?3 6 ?4 2 ?4 8 ?5 4 ?6 0 0x80 0x40 0x20 0x10 0x08 0x04 0x02 0x01 ref level 0.000db /div 6.000db marker 1 000 000.000hz mag (a/r) ? 8.918db start 1 000.000hz stop 1 000 000.000hz f i gure 17. g a in vs. f r equ e nc y vs. c o d e , r ab = 5 k? 1k 10k 100k 1m 0 ?6 ?12 ?18 ?24 ?30 ?36 ?42 ?48 ?54 ?60 0x80 0x40 0x20 0x10 0x08 0x04 0x02 0x01 ref level 0.000db /div 6.000db marker 510 634.725hz mag (a/r) ?9.049db start 1 000.000hz stop 1 000 000.000hz f i gure 18. g a in vs. f r equ e nc y vs. c o d e , r ab = 10 k? 1k 10k 100k 1m 0 ?6 ?1 2 ?1 8 ?2 4 ?3 0 ?3 6 ?4 2 ?4 8 ?5 4 ?6 0 0x80 0x40 0x20 0x10 0x08 0x04 0x02 0x01 ref level 0.000db /div 6.000db marker 100 885.289hz mag (a/r) ? 9.014db start 1 000.000hz stop 1 000 000.000hz f i gure 19. g a in vs. f r equ e nc y vs. c o d e , r ab = 50 k? 1k 10k 100k 1m 0 ?6 ?1 2 ?1 8 ?2 4 ?3 0 ?3 6 ?4 2 ?4 8 ?5 4 ?6 0 0x80 0x40 0x20 0x10 0x08 0x04 0x02 0x01 ref level 0.000db /div 6.000db marker 54 089.173hz mag (a/r) ? 9.052db start 1 000.000hz stop 1 000 000.000hz f i gure 20. g a in vs. f r equ e nc y vs. c o d e , r ab = 10 0 k?
ad5161 rev. 0 | page 10 of 20 10k 100k 1m 10m ?5.5 ? 6.0 ?6.5 ?7.0 ?7.5 ?8.0 ?8.5 ?9.0 ?9.5 ? 10.0 ? 10.5 ref level ?5.000db /div 0.500db start 1 000.000hz stop 1 000 000.000hz r = 5k ? r = 10k ? r = 50k ? r = 100k ? 5k ? ? 1.026 mhz 10k ? ? 511 mhz 50k ? ? 101 mhz 100k ? ? 54 mhz f i gure 21. C3 db bandwidth @ code = 0x80 frequency (hz) 10k 100 100k 1m 1k 0 20 40 60 p s rr (db) code = 0x80, v a = v dd , v b = 0v psrr @ v dd = 3v dc 10% p-p ac psrr @ v dd = 5v dc 10% p-p ac fi g u r e 2 2 . p s r r v s . fr e q u e n c y i dd ( a) frequency (hz) 10k 800 700 600 500 400 300 900 200 100 100k 1m 10m 0 code = 0x55 code = 0xff v dd = 5v f i g u re 23. i dd vs . f r e q ue nc y vw clk ch 1 200mv b w ch 2 5.00 v b w m 100ns a ch2 3.00 v 1 2 f i gure 2 4 . di g i ta l f eedthro u g h vw cs ch 1 100mv b w ch 2 5.00 v b w m 200ns a ch1 152mv 1 2 v a = 5v v b = 0v f i g u re 25. m i ds c a l e gli t ch, cod e 0x 80 C 0 x 7 f vw cs ch 1 5.00v b w ch 2 5.00 v b w m 200ns a ch1 3.00 v 1 2 v a = 5v v b = 0v f i g u re 26. lar g e s i g n al s e t t l ing ti m e , code 0x ffC0x 00
ad5161 rev. 0 | page 11 of 20 test circuits f i gur e 27 t o f i gur e 35 il l u s t ra t e th e t e s t cir c ui ts tha t def i n e t h e t e st con d i t io ns us e d in t h e p r o d uc t sp e c if ic a t i o n t a b l es. v ms a w b dut v + = v dd 1lsb = v + / 2 n v+ f i gure 27. t e s t c i rc uit for p o tenti o meter d i v i de r n o nl in ea rit y e r r o r (inl, dnl) no connect i w v ms a w b dut f i gure 28. t e s t c i rc uit for r e s i s t or p o s i tion non l i n e a r i t y e rror (r heo s ta t o p er a t ion; r - inl, r - dnl) v ms1 i w = v dd /r nominal v ms2 v w r w = [v ms1 ? v ms2 ]/ i w a w b dut f i gur e 2 9 . t e st c i r c ui t fo r wi p e r resi st a n c e ? v ? v ? v ? v ms % dd % pss (% / %) = v+ = v dd 10% psrr (db) = 20 log ms dd ( ) v dd v a v ms a w b v+ f i gure 30. t e st c i rc uit for p o w e r sup p l y s e nsit ivit y ( p ss, pssr) op279 w 5v b v out offset gnd offset bias a dut v in f i gure 31. t e s t c i rc uit for in ve r t ing g a in b a v in op279 w 5v v out offset gnd offset bias dut f i gure 32. t e s t c i rc uit for no ni n v er t i n g g a in +15v ?15v w a 2.5v b v out offset gnd dut ad8610 v in f i gure 33. t e s t c i rc uit for g a in v s . f r eq uenc y w b v ss to v dd dut i sw code = 0x00 r sw = 0.1v i sw 0.1v f i gu r e 3 4 . t e st ci r c u i t fo r i n cr em en ta l on re si sta n c e w b v cm i cm a nc gnd nc v ss v dd dut nc = no connect f i gure 35. t e s t c i rc uit for co m m o n -mode l e ak age cu rre nt
ad5161 rev. 0 | page 12 of 20 spi interface table 5. ad51 61 s e rial da ta-word format b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 m s b l s b 2 7 2 0 sdi clk cs v out 1 0 1 0 1 0 1 0 d7 d6 d5 d4 d3 d2 d1 d0 rdac register load f i gur e 3 6 . ad51 61 sp i int e r f a c e t i mi ng di a g r a m (v a = 5 v , v b = 0 v , v w = v ou t ) t csho t css t cl t ch t ds t csw t s t cs1 t csh1 t ch sdi clk cs vout 1 0 1 0 1 0 v dd 0 1lsb (data in) dx dx f i gure 37. spi inte r f ac e d e tai l ed tim i n g d i ag r a m ( v a = 5 v , v b = 0 v , v w = v ou t )
ad5161 rev. 0 | page 13 of 20 i 2 c interface table 6 . write mode s 0 1 0 1 1 0 a d 0 w a x rs sd x x x x x a d7 d6 d 5 d 4 d 3 d 2 d1 d0 a p slave address byte instruction byte data byte table 7. read mode s 0 1 0 1 1 0 a d 0 r a d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 a p slave address byte data byte s = s t a r t c o n d i t io n p = s t o p c o n d i t io n a = a c k n o w le dge x = d o n t c a r e w = w r i t e r = re ad rs = res e t w i p e r t o mids cale 80 h s d = sh u t do w n co nne c t s wi p e r to b ter m ina l and o p e n cir c ui ts a t e r m i n a l . i t do es n o t cha n ge con t e n ts o f wi p e r re g i ste r . d7, d6, d5, d4, d3, d2, d1, d0 = d a t a bi ts t 1 t 3 t 4 t 2 t 7 t 8 t 9 ps p s t 10 t 5 t 9 t 8 scl sd a t 2 t 6 f i g u re 38. i 2 c inter f a c e d e ta il ed ti mi ng di a g r a m scl frame 1 frame 2 start b master ac b ad5161 slave address bte stop b master instruction bte sda 0 1 0 1 1 0 ad0 r/w r s 1 9 19 d7 d6 d5 d4 d3 d2 d1 d0 ac b ad5161 frame 3 data bte 1 9 ac b ad5161 sd fi g u r e 3 9 . w r it ing t o the rd a c regist er no ac b master scl sda 0 1 0 1 1 0 ad0 r/w d7 d6 d5 d4 d3 d2 d1 d0 1 9 1 9 frame 1 frame 2 start b master ac b ad5161 slave address bte rdac register stop b master f i g u re 40. r e ad ing d a t a f r o m a p r ev i o us ly s e lec t ed r d a c r e g i s t er in writ e m o de
ad5161 rev. 0 | page 14 of 20 ope ration the ad5161 is a 256-p o si tion dig i t a l l y co n t r o l l ed va r i ab le re s i stor ( v r ) d e v i c e . an in t e r n al p o w e r - o n p r es et places t h e wi p e r a t mids cale d u r i n g p o w e r - on, w h ich sim p l i f i es t h e f a u l t condi t i on r e co v e r y at p o w e r- u p . programming the variable resi stor rheostat ope r ation the n o minal r e sis t a n ce o f the rd a c be tw e e n t e r m inals a and b is a v a i la b l e in 5 k?, 10 k?, 50 k?, a nd 100 k? . th e f i nal tw o o r t h r e e dig i ts of t h e p a r t n u m b er det e r m i n e t h e n o minal r e sis t a n c e val u e , e . g., 10 k? = 10 ; 50 k? = 50. the n o minal re s i st anc e ( r ab ) o f th e vr has 2 56 co n t ac t p o in ts acces s e d b y t h e w i p e r t e r m i n al , pl us t h e b ter m inal co n t ac t. the 8- b i t da t a in t h e rd a c l a tc h is deco ded t o s e lec t on e o f the 256 p o s s i b le s e t t i n gs. a ssu me a 10 k? p a r t is us e d , t h e w i p e r s f i rst co nne c t io n s t a r ts a t t h e b t e r m i n al fo r da t a 0x0 0 . sin c e t h er e is a 60 ? wi p e r con t ac t r e sis t a n ce , suc h co nn ec tion yie l ds a mini m u m o f 60 ? r e sist a n ce b e tw e e n ter m ina l s w an d b . t h e s e con d co n n e c t i o n is t h e f i rst t a p p o in t, w h ich c o r r esp o n d s t o 99 ? (r wb = r ab /256 + r w = 39 ? + 60 ?) f o r da ta 0x01. the thir d conn e c tio n is the n e xt ta p p o in t, r e p r es en tin g 177 ? (2 39 ? + 60 ?) f o r da ta 0x0 2 , a n d s o o n . e a c h ls b da ta val u e in cr e a s e m o v e s t h e w i p e r u p t h e r e sis t o r ladder un t i l t h e l a s t t a p p o in t is r e ac hed a t 9961 ? (r ab C 1 ls b + r w ). f i gur e 41 s h o w s a sim p lif i e d di ag ra m o f t h e e q u i valen t rd a c c i r c ui t w h er e t h e l a st re s i stor st r i ng w i l l not b e a c c e ss e d ; t h e r e f ore, t h e r e is 1 l s b les s o f th e n o minal r e sis t a n ce a t f u l l s c ale in addi tion t o t h e wi p e r r e sist an ce. b rdac latch and decoder w a r s r s r s r s sd bit d7 d6 d4 d5 d2 d3 d1 d0 f i gur e 4 1 . ad51 61 e q ui v a le nt rd a c cir c ui t t h e g e n e ral eq ua ti o n d e t e rm in in g th e d i g i tall y p r ogra m m e d o u t p u t r e s i s t a n ce bet w een w a n d b i s w ab wb r r d d r + = 256 ) ( ( 1 ) w h er e d is t h e decimal e q ui val e n t o f the b i na r y co de lo aded in t h e 8- b i t r d a c r e g i s t er , r ab is th e e n d- to -e n d resist a n ce, an d r w is th e wi p e r r e sis t a n c e co n t r i b u t e d b y th e on r e sis t an ce o f th e in t e rn al swi t c h . i n s u mma r y , if r ab = 10 k? a n d t h e a t e r m ina l is o p en c i rc u i te d, t h e f o l l ow i n g output r e s i st an c e r wb will be set f o r th e indic a te d r d a c la tch co des. table 8. codes and correspo nding r wb resi stance d (dec.) r wb (?) output state 255 9,961 full scale (r ab C 1 lsb + r w ) 1 2 8 5 , 0 6 0 m i d s c a l e 1 9 9 1 l s b 0 60 zero scale (wiper contact resistance) n o t e tha t in t h e zer o -s cale con d i t io n a f i ni t e wi p e r r e sis t a n c e of 60 ? is p r es en t. c a r e s h o u ld b e t a k e n t o li mi t t h e c u r r en t f l o w b e tw e e n w and b in t h is st a t e to a max i m u m p u ls e c u r r en t o f n o m o r e tha n 2 0 ma. o t her w is e , deg r ada t ion or p o s s i b le des t r u c t io n o f th e in t e r n al s w i t c h co n t ac t can o c c u r . si mi l a r to t h e me ch ani c a l p o te n t i o me te r , t h e re s i st a n c e of t h e rd a c bet w een th e wi per w a n d t e rm i n al a als o p r od uces a d i g i t a l l y c o nt r o l l e d c o mp l e m e nt a r y r e s i s t a n c e r wa . w h en t h es e t e r m ina l s a r e us e d , t h e b t e r m in a l ca n b e op e n e d . s e t t in g t h e r e sis t a n c e val u e fo r r wa st a r ts a t a max i m u m va lue o f r e sist a n ce a n d de cr e a s e s as t h e da t a lo ade d in t h e la t c h i n cr e a s e s in va l u e . the ge n e ra l e q u a t i o n fo r t h is o p era t io n is w ab wa r r d d r + ? = 256 256 ) ( (2) fo r r ab = 10 k? a n d t h e b t e r m inal o p en c i r c ui ted , the f o l l ow i n g output re s i st anc e r wa wi l l b e s e t fo r t h e indic a te d rd a c l a t c h co des. table 9. codes and correspo nding r wa re sistance d (dec.) r wa (?) output state 2 5 5 9 9 f u l l s c a l e 1 2 8 5 , 0 6 0 m i d s c a l e 1 9 , 9 6 1 1 l s b 0 1 0 , 0 6 0 z e r o s c a l e t y p i cal de vice to device ma t c hin g is p r o c es s lo t dep e n d en t and ma y va r y b y u p t o 30%. si n c e t h e r e sis t an c e e l e m e n t is p r o c es s e d in thin f i lm t e chn o log y , th e c h a n g e in r ab wi t h t e m p era t ur e has a v e r y lo w 45 p p m/ c t e m p er a t ur e co ef f i cien t.
ad5161 programm ing t h e po tent iomet e r divi der voltage output operation th e di g i t a l p o te n t i o me te r e a s i ly ge ne r a te s a volt age d i v i de r a t w i p e r - to - b a n d w i p e r - to - a prop or t i ona l to t h e i n put volt age a t a - t o -b . u n l i k e t h e p o la r i ty o f v dd t o gnd , whic h m u s t be p o s i t i ve, vol t ag e ac ro ss a - b , w - a , and w - b c a n b e a t e i t h e r po l a ri t y . i f ig n o r i n g t h e e f fe c t o f t h e w i p e r r e sist a n ce fo r a p p r o x im a t ion, co nne c t in g t h e a t e r m ina l t o 5 v a n d t h e b ter m ina l t o g r o u nd p r o d uces a n ou t p u t v o l t a g e a t the wi p e r - t o -b star tin g a t 0 v u p t o 1 ls b les s than 5 v . e a c h l s b o f v o l t a g e is eq u a l t o th e v o l t a g e a p p l ie d acr o s s t e r m inal ab divided b y t h e 256 p o si t i o n s o f t h e p o t e n t iom e t e r divider . th e ge n e ral e q u a t i o n def i nin g t h e output vo lt ag e at v w wi th r e sp e c t t o g r o u n d f o r a n y valid in p u t v o l t a g e a p plie d t o t e r m ina l s a and b is b a w v d v d d v 256 256 256 ) ( ? + = ( 3 ) f o r a m o r e acc u ra t e c a lc u l a t ion, w h ich i n cl udes t h e ef fe c t o f wi p e r r e sist an ce, v w , c a n b e f o u n d a s b wa a wb w v d r v d r d v 256 ) ( 256 ) ( ) ( + = ( 4 ) o p er a t ion o f t h e dig i t a l p o ten t i o m e ter in t h e divider m o d e re su lt s i n a more a c c u r a te o p e r at i o n ove r te m p e r a t u r e. u n l i ke t h e rh e o s t a t m o de , t h e o u t p u t vol t a g e is de p e n d en t mainly o n th e ra ti o o f th e in t e rn al r e s i s t o r s r wa and r wb and n o t t h e a b s o l u t e v a l u es. ther efo r e , t h e tem p er a t ur e dr if t r e d u ces t o 15 p p m /c. pin selectable digital interface the ad5161 p r o v ides the f l exi b ili t y o f a s e lec t a b le in t e r f ace . w h en t h e dig i t a l in t e r f ace s e le c t (d is) p i n is t i e d lo w , t h e sp i m o de is en ga ge d . w h en t h e d i s p i n is t i e d hi g h , t h e i 2 c mo de is en ga g e d . spi compatible 3-w re serial bus (dis = 0) i the ad5161 con t a i n s a 3 - wir e s p i co m p a t ib le dig i t a l in t e r f ace (s d i , cs , a n d c l k ) . t h e 8 - b i t s e r i a l w o r d m u s t b e l o a d e d m s b f i rs t. the fo r m a t o f t h e w o r d is s h own i n t a b l e 5. the p o si t i ve-e dg e s e n s i t i v e cl k in p u t r e q u ir e s cle a n t r a n si t i on s t o a v o i d c l o c k i ng in co r r ec t da ta in t o t h e s e r i a l in p u t r e g i st er . s t a nda rd log i c fa milies w o rk w e l l . i f m e c h a n ical swi t ch es a r e us ed f o r p r o d uc t eval ua tio n , t h e y s h o u ld be deb o un ce d b y a f l ip - f l o p or ot he r su it abl e me an s . w h e n cs is l o w , t h e cl o c k lo ads da t a in t o t h e s e r i al r e g i s t er o n eac h p o si t i v e c l o c k edge (s ee f i gur e 36). the da t a s e t u p a nd da t a h o ld t i m e s i n t h e sp e c i f ica t ion t a b l e det e r m in e t h e valid timin g r e q u ir em en ts. the ad5161 us es a n 8 - bit s e r i a l i n put d a t a re g i ste r w ord t h a t i s t r ans f e r re d to t h e i n t e rn al rd a c r e gi s t e r w h en th e cs line r e t u r n s to log i c hig h . e x t r a m s b bit s are i g nore d. d a isy-chain operation the s e r i al da t a o u t p u t (s d o ) p i n con t a i n s an o p en-dra in n - ch a n nel f e t . t h i s output re q u i r e s a pu l l - u p re s i stor i n ord e r t o tra n sf er da t a t o th e n e xt p a c k a g e s s d i p i n. this al lo ws f o r d a i s y- c h a i ni n g sev e ral rd a c s f r o m a s i n g l e p r oc e s so r se ri al d a t a li ne. t h e pu l l -u p r e sisto r ter m ina t ion vol t a g e can b e l a rger th a n t h e v dd s u p p l y v o l t a g e . i t is r e co mmen d e d t o in cr eas e t h e cl o c k p e r i o d w h e n u s i n g a pu l l - u p re s i stor to t h e sdi pi n of t h e f o l l o w in g de vic e be ca us e c a p a ci ti v e lo adin g a t t h e da isy-c h a i n n o de s d o-s d i betw een devices ma y in d u ce tim e de l a y t o s u bs e q uen t de vices. u s ers sh o u l d b e a w a r e o f this p o t e n t ial p r ob lem t o ac hiev e da ta tran sf er s u cces s f u l l y (see f i gur e 42). i f tw o ad5161s a r e da isy-c h a i n e d , a t o tal o f a t least 16 b i ts o f da t a is r e q u ir e d . th e f i rs t eig h t b i ts, c o m p lyin g w i t h t h e fo r m a t s h own in t a b l e 5, g o t o u2 a nd th e s e con d eig h t b i ts wi t h the s a me f o r m a t g o t o u1. cs s h o u l d b e k e p t lo w un til al l 16 b i ts a r e c l oc k e d in t o th ei r r e s p ecti v e se r i al r e gi s t e r s . a f t e r th i s , cs is pu l l e d hi g h to c o m p l e te t h e op e r a t i o n and l o ad t h e r d a c l a tc h . i f th e d a ta w o r d d u ri n g th e cs lo w p e r i o d is g r ea t e r tha n 16 b i ts, a n y a ddi t i ona l ms bs wi l l b e dis c a r de d . ad5161 ad5161 u2 c u1 cs sdi clk clk sdo cs clk sdi sdo sc mosi v dd r p 2.2k ? f i gure 42. d a isy- chain c o nfigur ation i 2 c co mpatible 2-w re seria l bus (dis = 1) i the ad5161 can als o be con t r o l l ed via a n i 2 c c o m p a t i b le s e r i al b u s wi th d i s tie d h i g h . th e rd a c s a r e co nn ec t e d t o th i s b u s as sl a v e d e v i c e s . the f i rs t b y t e o f th e ad5161 is a s l a v e addr es s b y t e (s ee t a b l e 6 a nd t a b l e 7). i t has a 7- b i t sl a v e addr ess and a r/ w bit . t h e s i x ms bs o f th e sla v e addr es s a r e 0 10110, a n d t h e fol l o w in g b i t is det e r m i n e d b y t h e st a t e o f t h e a d 0 p i n o f t h e de v i ce . a d 0 al lo ws t h e us er t o place u p t o t w o o f t h e i 2 c com p a t i b le de vices on o n e bu s . the 2- wir e i 2 c s e r i a l bu s proto c o l op e r a t e s a s f o l l ow s : 1. the mas t er ini t i a t e s da t a t r an sfer b y es t a b l is hing a st a r t co ndi tion, which is w h en a hig h -t o-lo w tra n s i t i o n o n t h e s d a line o c c u rs while scl is hig h (s ee f i gur e 3 9 ). th e fol l o w in g b y t e i s t h e sla v e addr es s b y t e , w h ich co n s is ts o f rev. 0 | page 15 of 20
ad5161 rev. 0 | page 16 of 20 t h e 7- b i t sla v e addr es s fol l o w e d b y a n r/ w bi t ( t h i s bi t d e te r m i n e s w h e t he r d a t a w i l l b e re a d f rom or w r itte n to t h e sla v e de v i ce ). the s l a v e w h os e addr es s co r r esp o n d s t o t h e t r an smi t t e d addr ess r e sp onds b y p u l l in g t h e s d a l i n e lo w d u r i n g t h e nin t h clo c k p u ls e (t his is t e r m e d t h e ack n o w le dg e b i t). a t this s t a g e , al l o t h e r devices o n t h e b u s r e ma in idle while t h e s e lec t e d device wa i t s f o r da t a t o be wr i t t e n t o o r r e ad f r o m i t s s e r i a l r e g i s t er . i f t h e r/ w b i t is hig h , t h e mas t er wi l l r e ad f r o m t h e sla v e de v i ce . on t h e o t h e r hand , if t h e r/ w bit i s lo w , t h e mast er wi l l wr i t e t o t h e s l a v e de vi ce . 2. a wr i t e o p er a t i o n co n t a i n s a n ext r a in s t r u c t io n b y t e t h a t a r e ad o p er a t io n do es n o t co n t a i n. s u ch a n i n st r u c t io n b y te in wr i t e m o de fol l o w s t h e s l a v e addr es s b y t e . the f i rs t b i t (ms b ) o f t h e inst r u c t io n b y t e is a do n t ca r e . the s e cond ms b , rs, is th e mids cale r e s e t. a log i c hig h on t h is b i t m o v e s t h e w i p e r t o t h e cen t er t a p w h ere r wa = r wb . this fe a t ur e ef fe c t i v e l y wr i t es o v er t h e con t e n ts o f t h e r e gi s t e r , a n d th us , wh en ta k e n o u t o f r e se t m o de , th e rd a c wi l l r e ma i n a t mids ca le. the thir d m s b , s d , is a s h u t do wn b i t. a log i c hig h c a us es an op e n c i rc u i t a t te r m i n a l a w h i l e s h or t i ng t h e w i p e r to t e r m ina l b . this o p era t ion yie l d s a l m o st 0 ? i n rh e o st a t m o d e o r 0 v in p o t e n t iom e t e r m o d e . i t is im p o r t a n t t o n o t e t h a t t h e sh u t do w n o p era t io n do es n o t dist urb t h e con t e n ts of t h e re g i ste r . w h e n brou g h t out of sh ut d o w n , t h e p r e v io us s e t t in g wi l l b e a p plie d t o t h e r d a c . a l s o , d u r i n g sh u t do w n , ne w s e t t i n gs can b e p r o g r a mm e d . w h en t h e p a r t i s re tu r n e d f rom sh ut d o w n , t h e c o r r e s p o nd i n g v r se t t in g w i ll be a p p l i e d t o t h e rd a c . the r e ma i n der o f t h e b i ts i n t h e in s t r u c t io n b y t e a r e don t ca r e s (s ee t a b l e 6). 3 . a f te r ack n ow l e dg i n g t h e i n st r u c t i o n b y te, t h e l a st b y te i n w r i t e m o d e i s t h e da ta b y t e . d a ta i s tra n s m i t t e d o v e r th e s e r i al b u s in s e q u en ces o f nin e clo c k p u ls es (eig h t da ta b i ts f o l l owe d by an a c k n ow l e d g e bit ) . t h e t r ans i t i on s on t h e s d a line m u s t o c c u r d u r i n g the lo w p e r i o d o f scl an d r e ma in sta b le d u r i n g th e hig h p e r i o d o f scl (s e e t a b l e 6). 4. i n t h e r e a d m o de , th e da ta b y t e f o llo w s i m m e dia t e l y a f t e r t h e ack n o w le dg m e n t o f t h e s l a v e addr es s b y te . d a t a is t r a n smi t t e d o v er t h e s e r i al b u s in s e q u e n ces o f nin e c l o c k p u ls es (a s l ig h t dif f er en ce w i t h t h e wr i t e mo de , w h er e t h er e a r e eig h t da t a b i ts fol l o w e d b y a n ack n o w le dg e b i t). s i m i la r l y , th e tra n s i ti o n s o n t h e s d a lin e m u s t occur d u ri n g th e l o w pe ri od o f s c l a n d r e m a in s t a b l e d u ri n g th e hig h p e r i o d o f scl (s ee f i gur e 40). 5. w h en al l da ta b i ts ha v e been r e ad o r wr i t t e n, a s t o p co ndi tion is es t a b l ish e d b y t h e mas t er . a s t o p co n d i t ion is def i n e d as a lo w-to -hig h t r a n s i t i o n o n t h e sd a l i ne w h i l e scl is hig h . i n wr i t e mo de , t h e mas t er wi l l p u l l t h e sd a lin e hig h d u r i n g t h e t e n t h clo c k p u ls e t o es t a b l ish a st o p co ndi tion (s ee f i gur e 39). i n r e ad m o de , t h e mas t er wil l is s u e a n o a c k n o w le dg e fo r t h e nin t h clo c k p u ls e (i .e ., t h e s d a li ne r e ma i n s hig h ). the mas t er wi l l t h en b r in g t h e s d a line lo w befo r e th e t e n t h c l o c k p u ls e w h ic h g o es hig h t o es ta b l ish a s t o p co n d i t ion (s ee f i gur e 40). a r e p e a t e d wr i t e f u n c t i on g i v e s t h e us er f l exi b i l i t y t o u p da te t h e rd a c o u t p ut a n u m b er o f t i m e s a f ter addr essi ng a nd in s t r u c t in g t h e p a r t o n l y o n ce . dur i n g th e wr i t e c y c l e , eac h da t a b y te w i l l up d a te t h e r d a c out p ut . f o r e x am pl e, af te r t h e r d a c has ack n o w le dge d i t s sl a v e a ddress an d i n st r u c t io n b y tes, t h e r d a c out p ut w i l l up da te af te r t h e s e t w o b y te s . i f anot he r b y te is wr i t t e n t o t h e rd a c w h i l e i t is st i l l addr ess e d t o a sp e c if ic s l a v e device wi t h the s a m e in s t r u c t io n, this b y t e wil l u p da te the o u t p ut o f t h e s e le c t e d sla v e de vi ce . i f dif f er en t i n s t r u c t io n s a r e ne e d e d , t h e w r i t e mo d e h a s to st ar t ag ai n w i t h a n e w s l a v e addr ess, inst r u c t io n, an d d a t a b y te. simi l a rly , a r e p e a t e d r e a d f u n c tion o f th e rd a c is als o al lo w e d . readback rdac valu e the ad5161 al lo ws th e us er t o r e ad bac k t h e rd a c val u es in t h e r e ad m o de . refer t o t a b l e 6 a nd t a b l e 7 fo r t h e p r o g r a mmin g fo r m a t . mul t iple devic e s on one bu s f i gur e 43 s h o w s tw o ad5161 de vices on the s a m e s e r i al b u s. e a ch has a dif f er en t s l a v e addr e s s since t h e s t a t es o f t h eir a d 0 p i n s a r e dif f er en t. thi s al lo ws e a c h rd a c wi thin each device to b e w r itte n to or re a d f rom i n d e p e n d e n t ly . t h e m a ste r d e v i c e o u t p ut b u s li n e dr i v ers a r e o p en-dra i n p u l l -dow n s in a f u l l y i 2 c co m p a t i b le in t e r f ace . master ad5161 sda scl r p r p +5v +5v sda scl sda scl ad5161 ad0 ad0 f i g u re 43. m u lt ip le a d 51 61 d e v i ces on o n e i 2 c b u s
ad5161 rev. 0 | page 17 of 20 level shif ting for bi directio nal interface w h i l e m o s t legac y sys t em s ma y b e o p era t e d a t on e v o l t a g e , a n e w co m p o n en t m a y b e o p ti mized a t a n o t h e r . w h e n t w o sys t em s o p era t e t h e s a me sig n al a t t w o dif f er en t v o l t a g es, p r o p e r le v e l shif t i ng is n e e d e d . f o r in st a n c e , o n e can us e a 3.3 v e 2 pro m to i n te r f ac e w i t h a 5 v di g i t a l p o te n t i o me te r . a l e v e l shif t i ng s c h e m e is n e e d e d t o en a b le a b i dir e c t iona l co m m un ica t i o n so th a t t h e set t in g o f th e di gi ta l po t e n t i o m e t e r ca n b e sto r e d to a nd r e t r ie ve d f r o m t h e e 2 p r o m . f i gur e 44 s h o w s on e o f t h e im p l em en t a tio n s. m1 a nd m 2 ca n be an y n-chan n e l sig n a l f e t s , o r if v dd fal l s be lo w 2.5 v , lo w thr e s h old fet s s u c h as t h e fd v301n . e 2 prom ad5161 sda1 scl1 d g r p r p 3.3v 5v s m1 scl2 sda2 r p r p g s m2 v dd1 = 3.3v v dd2 = 5v d f i gure 44. l e vel s h if ting for o p e r at ion at d i ffe r e nt p o te ntials esd protection a l l d i g i t a l i n put s are prote c te d w i t h a s e r i e s i n put re s i stor an d p a r a l l el z e ne r e s d st r u c t u r e s s h ow n i n f i g u re 4 5 an d f i g u re 4 6 . this a p plies t o t h e dig i t a l in p u t p i n s s d i / s d a, clk/s c l, an d cs /ad0. logic 340 ? v ss f i g u re 45. e s d pr ot ec t i o n of d i g i t a l p i ns a,b,w v ss f i g u re 46. e s d pr ot ec t i o n of r e s i s t o r t e r m in als terminal voltage operating ra nge the ad5161 v dd a n d g n d p o w e r su p p ly def i n e s t h e b o u ndar y c o ndi t i ons for prop e r 3 - te r m i n a l di g i t a l p o te n t i o me te r o p era t ion. s u p p ly sig n als p r es en t o n t e r m inals a, b , a nd w t h a t e x ceed v dd o r gnd wil l be clam p e d b y the in ter n al f o r w a r d b i as e d dio d es (s ee f i gur e 47). a v d d b w v ss f i g u re 47. m a x i mu m t e r m i n a l v o lt ag es s e t by v dd and v ss power-up sequence sin c e t h e es d pr o t e c t i o n di o d e s limi t t h e v o lt ag e co m p l i an ce a t t e r m ina l s a, b , a nd w (s e e f i gu r e 47), i t is im p o r t a n t t o p o w e r v dd /gnd bef o r e a p p l yin g an y vol t a g e t o t e r m inals a, b , a nd w ; o t h e r w is e , th e dio d e wil l be f o r w a r d b i as e d s u ch tha t v dd wi l l b e p o w e r e d uni n te n t io na l l y an d m a y a f fe c t t h e r e st o f t h e us er s cir c ui t. th e id e a l p o w e r - u p s e q u en c e is in t h e fol l o w in g o r d er : gnd , v dd , d i g i t a l i n p u t s , a n d t h e n v a/ b / w . t h e r e l a t i ve ord e r of po w e ri n g v a , v b , v w , a n d t h e di g i t a l i n p u ts is no t im p o r t a n t as l o ng a s t h e y are p o we re d af te r v dd /gnd . layout and power supply b y passing i t is a g o o d p r ac tice t o em p l o y co m p ac t, minim u m lead len g t h la yo u t desig n . th e le ads t o t h e in p u ts sh o u ld be as dir e c t as pos s i b le wi th a m i n i m u m co n d uct o r le n g th . g r o u n d p a th s s h o u ld ha v e lo w r e sis t a n ce an d l o w ind u c t an ce . s i mil a rl y , i t is al s o a g o o d p r ac tice t o b y p a s s t h e p o w e r s u p p lies wi t h q u ali t y ca p a ci t o rs f o r o p tim u m sta b ili t y . s u p p l y leads t o th e de vice s h o u l d b e b y p a s s e d wi th dis c o r c h i p cer a mic c a p a ci t o rs o f 0.01 f t o 0.1 f . l o w es r 1 f t o 10 f ta n t al um o r e l ec tr ol ytic ca p a ci t o rs sh o u ld als o be a p p l ied a t t h e su p p lies t o mini mi ze an y t r a n sien t dist ur b a n c e an d lo w f r e q uen c y r i p p le ( s e e f i g u re 4 8 ) . n o te t h a t t h e d i g i t a l g rou n d s h ou l d a l s o b e j o i n e d re motely to t h e an a l o g g r ou nd a t one p o i n t to mi ni m i z e t h e g rou nd b o u n c e . ad5161 v dd c1 c3 gnd 10 f 0.1 f + v dd f i g u r e 4 8 . p o w e r su pp l y by pa s s i n g
ad5161 pin conf iguration and fu nction descriptions pin c o nfig uratio n 1 2 3 4 5 10 9 8 7 6 a b cs/ado sdo/nc sdi/sd a dd ad5161 top view (not to scale) w v dis gnd clk/s c l f i g u re 49. pin func ti on descrip t io ns table 10. p i n n a m e d e s c r i p t i o n 1 a a t e r m i n a l . 2 b b t e r m i n a l . 3 cs /ad0 cs : chip select input, active low. when cs returns high, data will be loaded into the dac register. ad0: programmable address bit 0 for multiple package decoding. 4 s d o / n c sdo: serial data output. open-drain transistor requires pull-up resistor. nc: no connect. 5 sdi/sda sdi: serial data input. sda: serial data input/ output. 6 clk/scl serial clock input. positive edge triggered. 7 g n d digital g r o u n d . 8 d i s digital interface select (spi/i 2 c s e lect). spi when dis = 0, i 2 c when dis = 1. 9 v dd positive power s u pply. 1 0 w w terminal. rev. 0 | page 18 of 20
ad5161 outline dimensions 0.23 0.20 0.17 0.80 0.40 8 0 0.15 0.00 0.27 0.17 0.95 0.85 0.75 seating plane 1.10 max 10 6 5 1 0.50 bs c 3.00 bsc 3 .00 bs c 4.90 bsc pin 1 compliant to jedec standards mo-187ba coplanarit y 0.10 f i gure 50. 1 0 -l ead m i ni s m al l o u tl ine p a ck ag e [msop ] (r m - 10) di me nsio ns sho w n i n mi ll im e t e r s ordering guide m o d e l r ab (?) temperature package descri ption package option branding ad5161brm5 5k C40c to +125c msop-10 rm-10 d0c ad5161brm5-rl7 5k C40c to +125c msop-10 rm-10 d0c ad5161brm10 10k C40c to +125c msop-10 rm-10 d0d ad5161brm10- rl7 10k C40c to +125c msop-10 rm-10 d0d ad5161brm50 50k C40c to +125c msop-10 rm-10 d0e ad5161brm50- rl7 50k C40c to +125c msop-10 rm-10 d0e ad5161brm100 100k C40c to +125c msop-10 rm-10 d0f ad5161brm100 -rl7 100k C40c to +125c msop-10 rm-10 d0f ad5161eval see note 1 evaluation boar d 1 th e evaluat i on board is s h ippe d with the 10 k ? r ab re si st or opt i on ; h o w e ver, t h e boa r d i s com p a t i b le wi t h a ll a v a i l a b le r e si st or va lu e opt i on s. the ad5161 con t a i n s 2532 tran sis t o r s. die size: 30.7 mil 76.8 mil = 2358 s q . mil . esd caution esd (electrostatic discharge) sensitive device. ele c trosta tic charg e s as high as 4000 v readily accumulate on the human body and test eq uipment and can discharge with out detection. although this product features proprietary esd protection circu i try, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. theref ore, prop er esd precautions a r e recommended to avoid perform a nce degradation or l o ss of functiona l ity. rev. 0 | page 19 of 20
ad5161 rev. 0 | page 20 of 20 notes ? 2003 analo g de vices, inc. all rights reserve d . tra d em arks and registered tra d emar ks are the proper ty o f th eir respectiv e c o mpan ies . c03435C0 C 5/03(0)

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